//`timescale 1ns / 1ps
module top_32bit;
    reg [31:0] A,B;
    reg [2:0] F;
    wire [31:0]R;

    initial begin
        A = 32'd23;
        B = 32'd12;
        F = 3'b000;
        # 2 F= 3'b001;
        # 2 F= 3'b010;
        # 2 F = 3'b011;
        # 2 F= 3'b101;
        # 2 F= 3'b100;
        
        # 5 A = 32'h235b;
        B = 32'h3423;
        F = 3'b000;
        # 2 F= 3'b001;
        # 2 F= 3'b010;
        # 2 F = 3'b011;
        # 2 F= 3'b101;  
        # 1 $stop;
    end

    ALU1 alu(.R(R),.A(A),.B(B),.F(F));
	initial
  	begin
    	$dumpfile("alu.vcd");
    	$dumpvars(0, alu);
  	end 
endmodule

module ALU1(R,A,B,F);
    input [31:0] A,B;
    input [2:0]F;
    output [31:0]R;
    wire [31:0]a1,a2,b1,b2,b3;
    assign a1 = F[0]? 32'd1:B;
    assign a2 = F[0]? 32'd1:B;
    assign b1 = A + a1;
    assign b2 = A - a2;
    assign b3 = A * B;
    assign R = F[2]? b3 : (F[1]? b2 : b1); 
endmodule
